Design of Scalable Hardware Test Generators for On-Line BIST

This paper briefly reviews on-line built-in self-test (BIST) and shows its importance in concurrent checking. Then a new approach for the design of deterministic BIST hardware test generators is presented. The approach uses high-level models of circuits to identify the classes of tests needed for complete coverage of faults. The test generator is then designed with the following goals: scalability, nearminimal error latency, and complete coverage of the modeled faults. Moreover, the test generators produced are simple and have low hardware overhead. Preliminary case studies of carry-lookahead adders, arithmetic logic units, and barrel shifters show the usefulness of this technique.